🚀 From Design to Chip

Phase 1: Registration & Orientation

Registration Opens: February 15, 2026
Last Date to Register: February 28, 2026
Orientation Date: March 2, 2026

• Open registration through ChipMonk platform
• Orientation sessions covering:
• Hackathon goals
• Expected deliverables
• Basics of IP quality and documentation

Phase 2: Problem Statement Release

Date: March 3, 2026 (via email)

• Curated problem statements released by ChipMonk
• Each problem statement includes:
• Functional requirements
• Interface expectations
• Verification expectations

Phase 3: Development Phase

Duration: March 3 – March 31, 2026

• RTL design
• Verification environment development
• Technical documentation
• Weekly mentor check-ins and review sessions

Phase 4: Submission

Submission Date: April 1, 2026 (GitHub Submission)

• RTL source code
• Verification code
• Test results & coverage reports
• Technical documentation

Phase 5: Evaluation & Demo

Presentation Dates: April 10–11, 2026 (At SAKEC)

• Design approach presentation
• Verification strategy explanation
• Learnings & challenges discussion

India’s semiconductor future depends not only on fabs but on indigenous IP ownership. This hackathon is designed to move students beyond simulations into real, reusable RTL development.

• Industry-aligned problem statements
• Reusable IP repository contribution
• Mentorship-driven design refinement
• Exposure to verification and documentation standards

• Industrial & Automotive-grade IPs
• Vision & Imaging IP blocks
• Audio & Signal Processing systems
• AI Hardware & RISC-V based system IP

Expected Output: Clean RTL + Simulation + Verification + Documentation

• Synthesizable RTL code
• Testbench & verification environment
• Waveform results
• Technical documentation (architecture + design decisions)
• Final presentation slides

UG (2nd year onwards) · PG (VLSI / Electronics / Embedded Systems) · RTL & Verification Enthusiasts